An approximate expression for the bandwidth $\omega_{-3 \mathrm{~dB}}$ is given in (4.152). In this example, the load capacitance is modest and the source resistance high, so the Miller effect is likely to be the major limitation in the amplifier's bandwidth. To maximize $\omega_{-3 \mathrm{~dB}}$ we wish to minimize the Miller capacitance $\mathrm{C}_{\mathrm{gd} 1}=\mathrm{C}_{\mathrm{ov} 1}$ which requires us to use a small device width, $W_1$. As we saw in Chapter 1 , this implies relatively large values of $\mathrm{V}_{\text {eff, } 1}$. However, to avoid mobility degradation (which would make it difficult to obtain the targeted gain), we restrict ourselves to a maximum effective gate-source voltage of

$$
\mathrm{V}_{\mathrm{eff}, 1}=\frac{1}{2 \theta}=\frac{1}{2 \cdot 1.7 \mathrm{~V}^{-1}} \cong 300 \mathrm{mV}
$$


If we ensure that $L_1<L_2$, then $r_{d s 2}>r_{d s 1}$ so that $R_2 \cong r_{d s 1}$ in (4.124). Hence, the dc gain $A_0 \cong-g_{m 1} r_{d s 1}$ is approximately equal to the intrinsic gain of $Q_1$,

$$
A_0 \cong-g_{m 1} r_{d s 1}=-\frac{2 I_{D 1}}{V_{e f f, 1}} \cdot \frac{1}{\lambda I_{D 1}}=-\frac{2 L_1}{\lambda L_1 V_{e f f, 1}}
$$

where we have made a coarse approximation in assuming $\mathrm{r}_{\mathrm{ds} 1}=1 / \lambda \mathrm{I}_{\mathrm{D} \text {-sat }} \cong 1 / \lambda \mathrm{I}_{\mathrm{D}}$. Substituting the value $\lambda \mathrm{L}_1=0.08 \mu \mathrm{~m} / \mathrm{V}$ from Table 1.5 along with $\mathrm{V}_{\text {eff }, 1}=300 \mathrm{mV}$ and $\left|\mathrm{A}_0\right|=20$ into (4.158) allows us to solve for the device length.

$$
L_1=\left|A_0\right| \lambda L_1 V_{\text {eff }, 1}=(20 / 2) \cdot 0.08 \mu \mathrm{~m} / \mathrm{V} \cdot 0.3 \mathrm{~V}=0.24 \mu \mathrm{~m}
$$


Note that increasing the drain current while maintaining $\mathrm{V}_{\mathrm{eff}, 1}=300 \mathrm{mV}$ will increase $\mathrm{g}_{\mathrm{m} 1}$ and reduce $\mathrm{r}_{\mathrm{ds} 1}$ roughly in proportion resulting in approximately the same gain but a smaller $\mathrm{R}_2$ in the denominator of $\omega_{-3 \mathrm{~dB}}$ in (4.152). Hence, bandwidth is maximized by using all of the available current. In this case, for a total power consumption of 1 mW and reserving $\mathrm{I}_{\text {bias }}=50 \mu \mathrm{~A}$ of current for the biasing transistor $\mathrm{Q}_3$,

$$
\mathrm{I}_{\mathrm{D} 1}=\frac{1 \mathrm{~mW}}{1.8 \mathrm{~V}}-50 \mu \mathrm{~A} \cong 500 \mu \mathrm{~A}
$$


From the desired drain current, gate length, and $\mathrm{V}_{\text {eff, } 1}$ we may compute the required gate width

$$
\begin{gathered}
I_{D 1}=\frac{1}{2} \mu_n C_{o x} \frac{W_1}{L_1} V_{e f f, 1}^2 \\
\Rightarrow W_1=\frac{2 I_{D 1} L_1}{\mu_n C_{o x} V_{e f f, 1}^2}=\frac{2 \cdot 500 \mu \mathrm{~A} \cdot 0.24 \mu \mathrm{~m}}{270 \mu \mathrm{~A} / V^2(0.3 V)^2} \cong 10 \mu \mathrm{~m}
\end{gathered}
$$

To ensure $L_2 » L_1$, we take $L_2=3 L_1=0.72 \mu \mathrm{~m}$. Since they have the same drain currents, the width of $Q_2$ may be conveniently taken 3 times that of $\mathrm{Q}_1$, although this is not critical.

$$
\mathrm{W}_2=3 \cdot 10 \mu \mathrm{~m}=30 \mu \mathrm{~m}
$$


Finally, $Q_3$ is sized to provide the desired current ratio in the current mirror formed with $Q_2$.

$$
\begin{gathered}
\mathrm{L}_3=\mathrm{L}_2=0.72 \mu \mathrm{~m} \\
\mathrm{~W}_3=\mathrm{W}_2 \cdot\left(\frac{50 \mu \mathrm{~A}}{500 \mu \mathrm{~A}}\right)=3 \mu \mathrm{~m}
\end{gathered}
$$